![Stacks Image p25899_n25893](Trilby_connectors_files/stacks-image-6398c09.png)
The TRILBY HAT is here !
A revolution in Raspberry Pi HAT functionality & pricing.
![Stacks Image 19500](Trilby_connectors_files/stacks-image-0de533c.jpg)
Item | Connector | Description |
---|---|---|
1 | B1 | Battery holder for real-time clock. Install CR1220 battery or equivalent with +ve terminal facing upwards, in order for the real-time clock to continue operating when the board is powered down. |
2 | J2 | SMA connector for VHF/UHF antenna |
3 | J4 | SMA connector for HF antenna |
4 | J457 | 3-pin audio PWM output header (pin 2 is GND, pin 1 and 3 are for the two audio channels) |
5 | J454 | USB mini connector Can be used to power the board and/or to program the FPGA from a personal computer |
6 | J456 | Power mode jumper Link pins 1 and 2 to power the Trilby board from Raspberry Pi Link pins 2 and 3 to power the Trilby board via its USB connector |
7 | J29 | 6-pin JTAG header which can be used to program the FPGA using a cable supplied by Lattice pin 1: +3.3V pin 2: TDI pin 3: TMS pin 4: TCK pin 5: TDO pin 6: GND |
8 | J451 | FPGA programming mode selection Do not install this jumper if FPGA is to be programmed using the USB port Install jumper when programming using a Lattice JTAG cable or from the Raspberry Pi |
9 | J450 | FPGA programming mode selection Install this jumper if programming the FPGA using the USB port or from the Raspberry Pi Remove jumper in order to program using a Lattice JTAG cable |
10 | J33 | FPGA PROGRAMING input. Short these two pins momentarily to trigger reloading of the FPGA firmware from the flash memory. |
11 | J30 | FPGA configuration mode, bit 0 (install jumper for normal operation) |
12 | J31 | FPGA configuration mode, bit 1 (do not install for normal operation) |
13 | J32 | FPGA configuration mode, bit 2 (install jumper for normal operation) |
14 | J26 | Install this jumper to enable the Raspberry Pi to write to the EEPROM |
15 | J458 | 24 pin GPIO Expansion header pin 1 and 2 are +5V supply pin 20, 23 and 24 are GND pin 22 is an active-low reset signal (short to GND to reset the FPGA) when using demo firmware all other pins are connected directly to IO pins on the FPGA |
T
Mission
![Stacks Image pp15588_n13828_n8615](Trilby_connectors_files/stacks-image-499da7d-1198x674.jpg)
![Stacks Image p15588_n13792](Trilby_connectors_files/stacks-image-528655d.png)
150kHz to 1000MHz+
Software Defined Radio
Software Defined Radio
![Stacks Image p15588_n13793](Trilby_connectors_files/stacks-image-c1deea7.png)
HF Up Converter
![Stacks Image p15588_n13794](Trilby_connectors_files/stacks-image-71419f1.png)
Real Time Clock
![Stacks Image p15588_n13801](Trilby_connectors_files/stacks-image-f19b1ea.png)
Dual Audio Output Channels / Stereo Capable
![Stacks Image p15588_n13804](Trilby_connectors_files/stacks-image-7530cb0.png)
4 Coloured LEDs
![Stacks Image p15588_n13807](Trilby_connectors_files/stacks-image-e8f8741.png)
GPIO FPGA Breakout Connector
![Stacks Image p15588_n13810](Trilby_connectors_files/stacks-image-c4a5c90.png)
Lattice ECP5-45 FPGA
![Stacks Image p15588_n13813](Trilby_connectors_files/stacks-image-e5351f0.png)
Use Standalone or with Raspberry Pi
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