Project Settings |
---|
Project Name | pll_24_to_96 | Implementation Name | syn_results |
Top Module | pll_24_to_96 | Pipelining | 0 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 50 | Disable I/O Insertion | 1 |
Clock Conversion | 1 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
7 |
1 |
0 |
- |
0m:02s |
- |
26/08/2015 09:00:43 |
(premap) | Complete |
2 |
0 |
0 |
0m:00s |
0m:00s |
83MB |
26/08/2015 09:00:47 |
(fpga_mapper) | Complete |
11 |
1 |
0 |
0m:01s |
0m:02s |
86MB |
26/08/2015 09:00:51 |
Multi-srs Generator |
Complete | | | | 0m:01s | | | 26/08/2015 09:00:45 |
Area Summary |
|
Register bits | 0 |
I/O cells | 0 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 0 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
System | 100.0 MHz | NA | 10.000 |
Optimizations Summary |
Combined Clock Conversion | 0 / 0 |
| |
|