#Build: Synplify Pro J-2015.03L, Build 030R, Apr 20 2015 #install: C:\lscc\diamond\3.5\synpbase #OS: Windows XP 5.1 #Hostname: GEMINI #Implementation: syn_results Synopsys HDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 32-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 32-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\lscc\diamond\3.5\synpbase\lib\lucent\ecp5u.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\lucent\pmi_def.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\umr_capim.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\scemi_pipes.svh" @I::"C:\lscc\diamond\3.5\cae_library\synthesis\verilog\ecp5u.v" @I::"C:\lscc\diamond\3.5\cae_library\synthesis\verilog\pmi_def.v" @I::"C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\pll_24_to_96.v" Verilog syntax check successful! File C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\pll_24_to_96.v changed - recompiling Selecting top level module pll_24_to_96 @N:CG364 : ecp5u.v(757) | Synthesizing module VHI @N:CG364 : ecp5u.v(761) | Synthesizing module VLO @N:CG364 : ecp5u.v(1696) | Synthesizing module EHXPLLL @N:CG364 : pll_24_to_96.v(8) | Synthesizing module pll_24_to_96 @W:CL168 : pll_24_to_96.v(23) | Pruning instance scuba_vhi_inst -- not in use ... At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 41MB peak: 42MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Aug 26 09:00:43 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 32-bit mode File C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\syn_results\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 36MB peak: 37MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Aug 26 09:00:43 2015 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Aug 26 09:00:43 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 32-bit mode File C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\syn_results\synwork\pll_24_to_96_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 36MB peak: 37MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Aug 26 09:00:45 2015 ###########################################################] Pre-mapping Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1176R, Built Apr 20 2015 17:11:44 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 56MB) Reading constraint file: C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\pll_24_to_96.fdc Linked File: pll_24_to_96_scck.rpt Printing clock summary report in "C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\syn_results\pll_24_to_96_scck.rpt" file @N:MF249 : | Running in 32-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 59MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 59MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 65MB peak: 65MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 65MB peak: 67MB) ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=56 set on top level netlist pll_24_to_96 Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------- System 100.0 MHz 10.000 system system_clkgroup ================================================================= Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 83MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Aug 26 09:00:47 2015 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 1176R, Built Apr 20 2015 17:11:44 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 56MB) @N:MF249 : | Running in 32-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 64MB peak: 65MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 65MB peak: 67MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 61MB peak: 83MB) Writing Analyst data base C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\syn_results\synwork\pll_24_to_96_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 83MB) Writing EDIF Netlist and constraint files J-2015.03L @N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 84MB peak: 85MB) Writing Verilog Simulation files Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 84MB peak: 85MB) Writing VHDL Simulation files Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 85MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 85MB) @W:MT246 : pll_24_to_96.v(59) | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @S |##### START OF TIMING REPORT #####[ # Timing Report written on Wed Aug 26 09:00:51 2015 # Top view: pll_24_to_96 Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\kf\epaper\Trilby_test\pll96\pll_24_to_96\pll_24_to_96.fdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 10.000 @N:MT286 : | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------- System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup ================================================================================================================ @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------- System System | 10.000 10.000 | No paths - | No paths - | No paths - ========================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------- PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 =================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------- PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 ================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 0.000 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : 10.000 Number of logic level(s): 0 Starting point: PLLInst_0 / CLKINTFB Ending point: PLLInst_0 / CLKFB The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - CLKFB_t Net - - - - 1 PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - ==================================================================================== ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 86MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 86MB) --------------------------------------- Resource Usage Report Part: lfe5u_25f-6 Register bits: 0 of 24288 (0%) PIC Latch: 0 I/O cells: 0 Details: GSR: 1 PUR: 1 VHI: 1 VLO: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 35MB peak: 86MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Wed Aug 26 09:00:51 2015 ###########################################################]